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net6 作业

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net6 作业

 

net6 作业

 

 

// This is a simple example.
// You can make a your own header file and set its path to settings.
// (Preferences > Package Settings > Verilog Gadget > Settings - User)
//
//        "header": "Packages/Verilog Gadget/template/verilog_header.v"
//
// -----------------------------------------------------------------------------
// Copyright (c) 2014-2021 All rights reserved
// -----------------------------------------------------------------------------
// Author : lingaitao 791347720@qq.com
// File   : net6.v
// Create : 2021-07-20 22:22:25
// Revise : 2021-07-20 22:22:25
// Editor : sublime text3, tab size (4)
// -----------------------------------------------------------------------------
module net6(
input  wire ia,
input  wire ib,
input  wire clk,
output reg  oc=0    );

always@(posedge clk) begin
    oc<=ia |ib;
end
endmodule
// This is a simple example.
// You can make a your own header file and set its path to settings.
// (Preferences > Package Settings > Verilog Gadget > Settings - User)
//
//        "header": "Packages/Verilog Gadget/template/verilog_header.v"
//
// -----------------------------------------------------------------------------
// Copyright (c) 2014-2021 All rights reserved
// -----------------------------------------------------------------------------
// Author : yongchan jeon (Kris) poucotm@gmail.com
// File   : tb_net6.v
// Create : 2021-07-20 22:28:17
// Revise : 2021-07-20 22:36:09
// Editor : sublime text3, tab size (4)
// -----------------------------------------------------------------------------
`timescale 1ns/1ns
module tb_net6();
reg clk;
reg ia,ib;
wire oc;
initial begin
    ia=0;
    ib=1;
    clk=0;
    #10 ia=1;
    #20 ib=0;
    #20 ia=0;
end

always #5 clk=~clk;
net6 tb_net6_inst(
.ia     (ia),
.ib     (ib),
.clk    (clk),
.oc        (oc)    );
endmodule

 


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